I assume you are placing the DM pin according to the respective DQS group. The DM pin need to place to the same group like DQS. For example, DM[0] need to place to same x8 DQ group of DQS[0].
What is meant by the <variation name> is the hierarchy path of the termination control block in your project.
Assuming all the DM pin placement is correct then I suspect the Quartus Error (175005) is due to a known issue problem in the Quartus II software version 12.1 and later. If more than one UniPHY-based memory controller is instantiated without OCT sharing, the fitter may assign some pins for every interface to one OCT control block. This will cause errors because only one OCT control block can drive a I/O bank.
To verify if this is the issue, in the Compilation Report, go to Fitter -> Resource Section -> Output pins and scroll to the row with the mem_* signal. Scroll to the right and verify which OCT control block the pin is assigned to.
I attach the screenshots of the example report here for your reference. You can see fitter assign some mem1_* signals(mem1_ca[*],mem1_ck*, etc.) to
termination control block in LP2_example_xxxx(highlighted in blue). Since there is no oct sharing, all the mem1_* pins should use termination control block in LP1_example_xxx.
As a workaround, please add following assignments in the QSF and re-compile your project and fitter can pass.
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