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Altera_Forum's avatar
Altera_Forum
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8 years ago

Cyclone V Hard Memory Controller MPFE bandwidth

I have a QSYS design which uses DDR memory. The DDR memory is clocked at 400Mhz in the Hard Memory Controller, and is 32 bits wide, so max bandwidth (not allowing any latency!) is 2*400,000,000*32 = ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

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Based on your calculation, you assume the efficiency is 100% which is impossible for a memory controller.

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True, the calculations expect 100% efficiency, but a) no figure is given for expected efficiency, and b) I suggest that I might be using 40% of the maximum efficiency, and if the MPFE design is that poor I'd be very surprised.