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Honored Contributor

8 years ago

Cyclone V Hard Memory Controller MPFE bandwidth

I have a QSYS design which uses DDR memory. The DDR memory is clocked at 400Mhz in the Hard Memory Controller, and is 32 bits wide, so max bandwidth (not allowing any latency!) is 2*400,000,000*32 = ...

Altera_Forum

Honored Contributor

7 years ago

I assume this is efficiency issue

This should be expected because the controller efficiency will drop when we are using more than one port (MPFE).

https://www.altera.com/support/support-resources/knowledge-base/solutions/rd10302012_952.html

Based on your calculation, you assume the efficiency is 100% which is impossible for a memory controller.

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Cyclone V Hard Memory Controller MPFE bandwidth

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