Cyclone V Avalon-MM Interface for PCIe Root Port Questions

To get a RC PCIe core working, you need to connect its Avalon interface to an upstream device such as processor. This processor will serve as the actual initiator which will send the data request to PCIe RC via the Avalon interface. The PCIe RC will have the the TLP, DLLP & PHY layers implemented.

To initiate a data transfer between RC and EP, the software/firmware at the processor side will initiate either a memory read or memory write to the EP device in question. The device driver in turn will kick start the SGDMA to get the data from system memory to the RC (n case of write) which will then form the TLPs and send them across to the EP via the PCIe lanes.

When the system with processor, RC and EP is powered on, the RC will automatically perform an enumeration to determine if there are any downstream EPs and devices. Once it finds an EP/Device it will start the link training and configuration automatically. But all of this has to be taken care of by the firmware in the system.

Even an RC needs a processor like Bus Master to initiate the data transfers from the application layer and RC cannot initiate data transfers by itself.

Hope this answers your questions.