Cyclone IV GX Platformdesigner PCIe Hard-IP Upstream Port Arbitration

Thanks for your answers.

Response:

Currently, the Cyclone IX GX PCIe Hard IP does not offer a feature to lower prioritize the txs. Instead, I will recommend to use the tx_ws signal which creates a DLLP transmission priority. Please check if this can be useful to your application.

You may refer to Pg B-22 (Figure B-19) in following user guide for some reference on using the tx_ws signal.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pci_express.pdf

Followup:

I am using the QSYS/Platformdesigner method. So i think i won't be able to use the tx_ws at all?

Response:

As explained above, one method is to use the tx_ws signal. Alternatively, you can use software to specify priority on servicing requested interrupts and use interrupts.

As for using config space or arbitration on the interface to specify priority, this has not be implemented or tested using our Hard IP before. Hence, its feasibility and implementation challenges is unknown.

Followup:

Currently the design is using two datapaths:

1. time critical: One datapath issues a MSI with an interval of x kHz => the isr handler fetches data from bar0.
2. lower priority: Two DMA controllers in the qsys design write/read data to the host memory over the txs port and issue MSIs when they are finished.

The issue is that reading data from the isr handler via bar0 gets delayed by the concurrently access of the DMA controllers. I also think that the MSIs requests will get delayed?

How could tx_ws help me in this design?