Cyclone IV GX Platformdesigner PCIe Hard-IP Upstream Port Arbitration

Hie, Please check my replies to all your questions. Question: Now i have the problem of arbitration/priorities between txs and bar ports. After reading the IP Compiler for PCIe Userguide, I still have no clue which port has a higher priority (also priorities between different bars would be interessting). Response: There is no priority specified between using Rx Master Module and TX Slave(TXS) Module. Hence, if you are using the AVMM bridge provided by the IP compiler, you can either use either the Rx Master or TXS to access the BAR addresses. The IP itself did not specify any prioritization between RX Master and TXS. Question: In my application the txs should have the lowest priority, so that the DMAs get throttled. As result a low latency read/write to bars should be possible. Response: Currently, the Cyclone IX GX PCIe Hard IP does not offer a feature to lower prioritize the txs. Instead, I will recommend to use the tx_ws signal which creates a DLLP transmission priority. Please check if this can be useful to your application. You may refer to Pg B-22 (Figure B-19) in following user guide for some reference on using the tx_ws signal. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pci_express.pdf Question: I read about PCIe's Virtual Channels, but as far as I know the Cyclone IV does only support one Virtual Channel, so no solution? Yes only one VC is supported. Question: Is there any way to setup arbitration/priorities between PCIe txs and bars: Using PCIe Configurationspace (Config of FPGA Endpoint / CPU Rootport? Adding Arbitration mechanism in Platform Designer between txs and Bars? Response: As explained above, one method is to use the tx_ws signal. Alternatively, you can use software to specify priority on servicing requested interrupts and use interrupts. As for using config space or arbitration on the interface to specify priority, this has not be implemented or tested using our Hard IP before. Hence, its feasibility and implementation challenges is unknown. Regards, Nathan