Cyclone IV GX PCIe Hard IP behaves differently on Intel Core I7 vs Xeon root complexes

Hi SharmaUmesh278 ,

Are repeated accesses to BAR-space offsets after boot expected from BIOS/UEFI, Windows PCI bus enumeration, or other background PCIe activity?
>> In our user guide mentioned that, the RX logic processes requests from the root complex, and that the Avalon-MM RX master issues the corresponding Avalon-MM read/write transactions into the FPGA fabric. It also states that some bridge register regions are typically intended for access by PCI Express processors only, and that the PCI Express root complex typically requires write/read access to certain mailbox registers. So the guide supports the idea that root-complex-originated accesses are normal
>> detail please refer to IP Compiler for PCI Express User Guide

Has anyone observed different behavior between Intel Core desktop root complexes and Xeon/server root complexes when using the Cyclone IV GX PCIe Hard IP?
>> Our PCIe IP is following PCI-SIG compliance
>> As long as the Laptop is PCI-SIG compliance, by right it shall be no problem.
>> But in your case, I would suggest to switch to another different host and check if the error is follow. I suspect is individual host issue.

Are there known interoperability issues between older Cyclone IV GX PCIe endpoints and modern Gen3/Gen4 server root complexes, even when the link successfully negotiates to Gen1 x1?
>> Are you using Gen1 design if I understand correctly ?
>> I would suggest to set the BIOS PCIe speed from "auto" into "gen1", I did experience certain brand of host actually cannot perform auto negotiation.

Is there a recommended way to distinguish firmware/OS-generated PCIe accesses from accesses generated by the application or function driver?
>>From what I understand , the RX block processes requests from the root complex, passes header information to the Avalon-MM master, and the RX master generates the corresponding Avalon-MM transactions to the connected slaves.

Regards,
Wincent_Altera