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MKwiec's avatar
MKwiec
Icon for New Contributor rankNew Contributor
2 years ago
Solved

Cyclone 10 GX Simulation Files

Certain ports and attributes are missing in the simulation outputs. On our current project we use Onespin to verify that the output does things consistently. We have differential IOs in the projec...
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  • RichardT_altera's avatar
    RichardT_altera
    2 years ago

    Below is engineering's feedback:

    ---

    Simulation netlist (which customer is using) is not meant for formal verification.

    having said that we should be including all parameters in the ATOM instances in simulation netlist.

    ---

    From engineering feedback, it seems that the simulation netlist generated is not meant for OneSpin formal verification.

    When formal verification is enabled(set_global_assignment -name ENABLE_FORMAL_VERIFICATION ON), I checked that these are the verilog netlist generated under the project directory:

    verification/

    rtl/ (This directory contains all rtl files)

    elaborated/ (Directory contains files used in RTL vs Elaborated Verification)

    synthesized/ (Directory contains files used in Elaborated vs Synthesized Verification)

    planned/ (Directory contains files used in Synthesized vs Planned Verification)

    placed/ (Directory contains files used in Planned vs Placed Verification)

    routed/ (Directory contains files used in Placed vs Routed Verification)

    retimed/ (Directory contains files used in Routed vs Retimed Verification)

    final/ (Directory contains files used in Routed/Retimed vs Finalized Verification)

    You could perform Formal Verification at each stage

    elaborated : To verify RTL vs elaborated netlist

    synthesized : To compare elaborated vs synthesized netlist

    planned: To compare synthesized vs planned netlist

    placed: To compare planned vs placed netlist

    routed: To compare placed vs routed netlist

    retimed: To compare routed vs retimed netlist

    final: To compare routed/retimed vs finalized netlist

    Will inform if there is further update from the engineering.

    Regards,

    Richard Tan

RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
2 years ago

Hi.

From the engineering standpoints regarding the missing differential_mode attribute:

-----

From the description above, I understand there to be two issues:

1. The differential_mode parameter is not written out.

2. The muxsel port is not shown unless it's connected.

If you can't provide the customer's RTL, can you attach or point me to a design that contains an atom with a muxsel port and an IO in differential mode?

If needed, please provide the IO standard assignment that should be used to generate the type of IO buffer that displays the problems above.

If I have a design containing an atom with a muxsel port and an IO with differential_mode=true, I can figure out why they may not be shown.

I was unable to re-synthesize the iostandards.v or iostandards_compare.v files you provided.

The iostandards_compare.v file shows the use of the differential_mode parameter. It looks like the new parameter format that has been introduced in 24.3.

Did you generate that on a recent Quartus build? If so, do you have access to the customer's source code?

-----

Is it possible to provide the design with the above information?

Regards,

Richard Tan