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MKwiec's avatar
MKwiec
Icon for New Contributor rankNew Contributor
2 years ago
Solved

Cyclone 10 GX Simulation Files

Certain ports and attributes are missing in the simulation outputs. On our current project we use Onespin to verify that the output does things consistently. We have differential IOs in the projec...
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  • RichardT_altera's avatar
    RichardT_altera
    2 years ago

    Below is engineering's feedback:

    ---

    Simulation netlist (which customer is using) is not meant for formal verification.

    having said that we should be including all parameters in the ATOM instances in simulation netlist.

    ---

    From engineering feedback, it seems that the simulation netlist generated is not meant for OneSpin formal verification.

    When formal verification is enabled(set_global_assignment -name ENABLE_FORMAL_VERIFICATION ON), I checked that these are the verilog netlist generated under the project directory:

    verification/

    rtl/ (This directory contains all rtl files)

    elaborated/ (Directory contains files used in RTL vs Elaborated Verification)

    synthesized/ (Directory contains files used in Elaborated vs Synthesized Verification)

    planned/ (Directory contains files used in Synthesized vs Planned Verification)

    placed/ (Directory contains files used in Planned vs Placed Verification)

    routed/ (Directory contains files used in Placed vs Routed Verification)

    retimed/ (Directory contains files used in Routed vs Retimed Verification)

    final/ (Directory contains files used in Routed/Retimed vs Finalized Verification)

    You could perform Formal Verification at each stage

    elaborated : To verify RTL vs elaborated netlist

    synthesized : To compare elaborated vs synthesized netlist

    planned: To compare synthesized vs planned netlist

    placed: To compare planned vs placed netlist

    routed: To compare placed vs routed netlist

    retimed: To compare routed vs retimed netlist

    final: To compare routed/retimed vs finalized netlist

    Will inform if there is further update from the engineering.

    Regards,

    Richard Tan

RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
2 years ago

Is this behaviour can be duplicated using the previous design provided (iostandards_compare.v)?
I am unable to compile those files. Could you shares a simplified Quartus project .qar ?
Thank you.


Regards,

Richard Tan

MKwiec's avatar
MKwiec
Icon for New Contributor rankNew Contributor
2 years ago

Using the files that I gave you should produce the same thing with the setting of:

set_global_assignment -name ENABLE_FORMAL_VERIFICATION ON

This produced a verification directory. Inside of this verification directory, inside of the verification directory it produced a .sv. I believe this is what you wanted me to look at. This sv contains the Verilog with the differential_mode set correctly. This model is a twentynm_ component. This is fine if this is the method that we need to go from here, from examining the differences between the two components in the atoms files, it is mostly just the names of them.

Getting you a .qar could take quite a bit, but I would think the engineer you talked to previously could answer this very easily. If I can produce a cyclone10gx by using twentynm models, this shouldn't be too much of an issue.

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    2 years ago

    Yes, you are right. They are the same, you can either use the twentynm_io_ibuf or the cyclone10gx_io_ibuf.


    Regards,
    Richard Tan