Cyclone 10 - DDR3 clock bank location

Hi,

We use a Cyclone 10 Gx on our board and we implement a DDR3. The EMIF pins are in the bank 2K/2J while the clock comes from the bank 2A.

Our project doesn't fit in quartus.

The message is :

Error(13110): PLL reference clock is constrained to an IO bank outside the bank(s) used by EMIF/PHYLite system(s)

So we added the altctrlclk IP between the clock and the EMIF and we tried every options.

Fit doesn't pass.

The message is :

Error(16765): Clock buffer "u0|altclkctrl_1|altclkctrl_1|System_altclkctrl_1_altclkctrl_2000_n7sv24a_sub_component|sd1" is incompatible with the required global signal types of its destination ports. Modify your design to change the clock buffer type for the specified signal or the required global signal type of the destination nodes.

Is there a solution to connect clock from bank 2A to EMIF bank 2K/2J ?

Is it mandatory to have the clock in the same bank as EMIF ?

Best regards