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PVanL's avatar
PVanL
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Cyclone® 10 GX Avalon®-ST Interface for PCI Express example Simulation

I have followed the recipy as described in "ug_a10_pcie_avst.pdf" , "Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon®-ST Interface for PCI Express* User Guide", and the configuration seems to have...
PVanL's avatar
PVanL
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Hi Tan Boon Chiek,


Thanks for the suggestion.

Anyway, the simulation ended in

# SUCCESS: Simulation stopped due to successful completion!
# Simulation passed

What about the other questions:

1/ Do you have a drawing with a block diagram of the various modules in the system setup? (more detailed than Figure 3 in the ug_dex_a10_pcie_avst_pdf document)

2/ The transcript references to Stratix II, Stratix III, IV and V. Does this matter when mapping this to the Cyclone10GX? ( i understand in a future version you will try to accomodate a cyclone only mapping)

Looking forward to your feedback.

BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

1. That is the only block diagram that we have for the example design. So, the answer is no.

2. Actually I sent the answer before. I paste it again here:

It is expected the transcript referring to other devices because some of the files are re-use and not change the device name accordingly. Anyway, this should be improved to avoid user confusion. I will channel this back to the development team.