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PVanL's avatar
PVanL
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5 years ago

Cyclone® 10 GX Avalon®-ST Interface for PCI Express example Simulation

I have followed the recipy as described in "ug_a10_pcie_avst.pdf" , "Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon®-ST Interface for PCI Express* User Guide", and the configuration seems to have...
BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

Hi Sir,

I tried to generate the example design in Quartus pro 18.0 and 20.1, both Quartus also able to generate the file under this path:

\pcie_example_design_tb\ip\pcie_example_design_tb\pcie_example_design_inst_board_pins_bfm_ip\altera_conduit_bfm_180\sim

As a quick hack, may I can upload the file here and see if you can copy it over the path and re-run the simulation.



PVanL's avatar
PVanL
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Hi Tan Boon Chiek,

Thanks for providing me the file. After loading, i got an microsoft error 0x80010135, which means something like "Path too long" or "name too long". (which is strange, because <255 characters). Anyway, i shortened the name to something shorter. Then i adapted the corresponding modelsim_files.tcl file.

This did not work. Eventually i had to replace in the 'lappend' command $QSYS_SIMDIR/.. with the full path name.

I had to do this with several modelsim_files.tcl file. It is really strange, because the files it is calling, are all there, and mostly they are found and compiled, but sometimes not. i give you the modelsim_files.tcl files that I modified. Do you have any idea what could be wrong? It is of course a stupid solution to work with a full file path.

It looks like the simulation works . It is now at 20 usec, and reported:

# INFO: 464 ns Completed initial configuration of Root Port.
# INFO: 3657 ns RP LTSSM State: DETECT.ACTIVE
# INFO: 4429 ns RP LTSSM State: POLLING.ACTIVE
# INFO: 17261 ns RP LTSSM State: DETECT.QUIET
# INFO: 17357 ns RP LTSSM State: DETECT.ACTIVE
# INFO: 17409 ns RP LTSSM State: DETECT.QUIET
# INFO: 17473 ns RP LTSSM State: DETECT.ACTIVE
# INFO: 18253 ns RP LTSSM State: POLLING.ACTIVE
# INFO: 20389 ns EP Link Speed change to: Gen1
# INFO: 20429 ns EP Link Speed change to: 0

According the user guide, see Figure 7. Partial Transcript from Successful Endpoint Avalon-ST PIO Simulation Testbench at page 7, only after 60 usec the reporting is finished.....How long should this simulation take in real time?

Do you have a drawing with a block diagram of the various modules in the system setup? (more detailed than Figure 3 in the ug_dex_a10_pcie_avst_pdf document)

The transcript references to Stratix II, Stratix III, IV and V. Does this matter when mapping this to the Cyclone10GX?

Looking forward to your feedback.

Regards, Pieter