Forum Discussion

Occasional Contributor

2 years ago

CXL type 3 design example Design Assistant Errors

In building the CXL Type 3 example design in Quartus Prime Version 23.1.0 Build 115 03/30/2023 SC Pro Edition I get some CDC errors. I do not see them with the 22.4 build. CDC-50001 - 1-Bit Asynch...

cxltyp3_memexp_ddr4_top-Results---8-of-87-Rules-Failed.zip14 KB

Transceiver

brian1211

Occasional Contributor

2 years ago

So the build should work fine in a system and shouldn't experience any CDC issues with the given errors correct?

Forum Discussion

CXL type 3 design example Design Assistant Errors

Recent Discussions

F-Tile Ethernet Hard IP (100G)

Cyclone® 10 GX Avalon®-ST Interface for PCI Express example Simulation

Agilex-7 AXI MCDMA for PCIe hang

Can't generate F-Tile Ethernet Hard IP Design Example

Avalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP Soft Reset and Hard Reset