CXL Type 3 Design Example 1.81 simulation issue

Hi,

I tried with Avery BFM 2.5b.h1 and the issue still persists. It also fails with the IP generated by Quartus 23.2, using the new out-of-order support:

UVM_INFO /shared/cxltyp3ddr_tb_23p1_acs.ooo/tb/verif/sequences/cxl_m2s_self_check_seq.svh(263) @ 514134.842ns: uvm_test_top.env0.apci_rc.sequencer@@cxl_m2s_self_check_seq [CXL_REPORT] Waiting for Read transaction 0
"/shared/ip_gen_23_2/intel_rtile_cxl_top_0_ed/intel_rtile_cxl_top_cxltyp3_ed/intel_rtile_cxl_top_190/sim/dcc_top.sv", 23: cxl_tb_top.dut.intel_rtile_cxl_top_inst.intel_rtile_cxl_top_0.PROTECTED.dcc_ptM2SReq_illegal_asrt: started at 514227505231fs failed at 514227505231fs
Offending '<Protected>'
Error: "/shared/ip_gen_23_2/intel_rtile_cxl_top_0_ed/intel_rtile_cxl_top_cxltyp3_ed/intel_rtile_cxl_top_190/sim/dcc_top.sv", 23: cxl_tb_top.dut.intel_rtile_cxl_top_inst.intel_rtile_cxl_top_0.PROTECTED.dcc_ptM2SReq_illegal_asrt: at time 514227505231 fs
>>>> Time=514227.505ns, ASSERT - DCC M2SReq PT illegal asserted
>>>> Op=M2SREQDCD_RSVD31, ReIssue=0, Hit=0, CurrSt=TAGSTATE_I, NxtSt=TAGSTATE_ILLEGAL
"/shared/ip_gen_23_2/intel_rtile_cxl_top_0_ed/intel_rtile_cxl_top_cxltyp3_ed/intel_rtile_cxl_top_190/sim/dcc_top.sv", 23: cxl_tb_top.dut.intel_rtile_cxl_top_inst.intel_rtile_cxl_top_0.PROTECTED.dcc_ptM2SReq_illegal_asrt: started at 514227505231fs failed at 514227505231fs
Offending '<Protected>'
Error: "/shared/ip_gen_23_2/intel_rtile_cxl_top_0_ed/intel_rtile_cxl_top_cxltyp3_ed/intel_rtile_cxl_top_190/sim/dcc_top.sv", 23: cxl_tb_top.dut.intel_rtile_cxl_top_inst.intel_rtile_cxl_top_0.PROTECTED.dcc_ptM2SReq_illegal_asrt: at time 514227505231 fs
>>>> Time=514227.505ns, ASSERT - DCC M2SReq PT illegal asserted
>>>> Op=M2SREQDCD_RSVD31, ReIssue=0, Hit=0, CurrSt=TAGSTATE_I, NxtSt=TAGSTATE_ILLEGAL

Thank you,

Ricardo