Forum Discussion

RicardoC's avatar
RicardoC
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

CXL Type 3 Design Example 1.81 simulation issue

Hi, The version 1.81 of the Design Example of the CXL Type 3, using Quartus 23.1 source files, does not behave as intended. The testbench supposedly issues MemWrites of 1500 cache lines, and reads t...
Cxl
JonWay_altera's avatar
JonWay_altera
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi there,

There is a patch for v1.8 Q23.1 at RDC link here: https://www.intel.com/content/www/us/en/secure/content-details/778346/intel-fpga-cxl-1-1-2-0-design-example-programming-files-for-quartus.html?wapkw=766413

Can you install this patch to Q23.1 --> confirm it has been installed correctly in Quartus version --> regenerate the Type 3 example design --> run simulation?

Let us know if that resolve your problem.

If not, please provide:
a) AVERY BFM version

b) VCS version

c) simulation rundir which should have logfiles, trackers and wave dump as well

Thanks.