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RicardoC's avatar
RicardoC
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

CXL Type 3 Design Example 1.81 simulation issue

Hi, The version 1.81 of the Design Example of the CXL Type 3, using Quartus 23.1 source files, does not behave as intended. The testbench supposedly issues MemWrites of 1500 cache lines, and reads t...
Cxl
JonWay_C_Intel's avatar
JonWay_C_Intel
Icon for Frequent Contributor rankFrequent Contributor
3 years ago

Hi there,

There is a patch for v1.8 Q23.1 at RDC link here: https://www.intel.com/content/www/us/en/secure/content-details/778346/intel-fpga-cxl-1-1-2-0-design-example-programming-files-for-quartus.html?wapkw=766413

Can you install this patch to Q23.1 --> confirm it has been installed correctly in Quartus version --> regenerate the Type 3 example design --> run simulation?

Let us know if that resolve your problem.

If not, please provide:
a) AVERY BFM version

b) VCS version

c) simulation rundir which should have logfiles, trackers and wave dump as well

Thanks.

  • RicardoC's avatar
    RicardoC
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    Hi,

    Thank you for the suggestion, but our Quartus 23.1 was updated with patch 0.08 back in May to 23.1.0.115.

    a) Avery version: 2.5a

    b) VCS: P-2019.06-SP2-6

    c) The complete run directory is 53GB large, mostly because of the waveforms and sim databases. I have attached all logs and trackers with the exception of the phy tracker, since it is 230MB large when compressed. Let me know if you need this file, so it can be broken down into smaller chunks and uploaded in multiple posts.

    Thank you,

    Ricardo