Forum Discussion
RicardoC
Occasional Contributor
3 years agoCXL Type 3 Design Example 1.81 simulation issue
Hi, The version 1.81 of the Design Example of the CXL Type 3, using Quartus 23.1 source files, does not behave as intended. The testbench supposedly issues MemWrites of 1500 cache lines, and reads t...
JonWay_altera
Frequent Contributor
3 years agoHi there,
Can you also share the sim logs for 1.7 version of the Design Example using the Quartus 22.4 source code works correctly?
I spoke with the FAE. Can you also attach the modified tb/tests/cxl_base_test.sv, so we can understand how the failing MACRO was disabled?
Thanks.
- RicardoC3 years ago
Occasional Contributor
Hi,
Here are the files you requested.
Thank you,
Ricardo