Forum Discussion
RicardoC
Occasional Contributor
Occasional ContributorCXL IP Debug Toolkit
Hello, An Intel development kit DK-DEV-AGI027R1BES with the CXL Type 3 Example Design image causes an AMD Siena architecture system to reboot when a single write is issued. The information extracted...
KaranPathak
New Contributor
New ContributorHi,
I recently bought the CXL Type 3 IP from Altera/Arrow. I would like to have access to the user guide for putting the CXL type 3 design onto Agilex 7 series FPGA (R-tile). Can you tell me how to get the access to the guide below: belo https://www.intel.com/content/www/us/en/secure/content-details/795866/intel-agilex-7-r-tile-compute-express-link-cxl-1-1-2-0-fpga-ip-user-guide.html?DocID=795866 ?
