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RicardoC's avatar
RicardoC
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

CXL IP Debug Toolkit

Hello, An Intel development kit DK-DEV-AGI027R1BES with the CXL Type 3 Example Design image causes an AMD Siena architecture system to reboot when a single write is issued. The information extracted...
Cxl
zutalors's avatar
zutalors
Icon for New Contributor rankNew Contributor
1 year ago

For the record I have no issues with the PCIe example design for the board, it comes up with Gen5x16 each time so the physical layer should be ok.