Forum Discussion

RicardoC's avatar
RicardoC
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

CXL IP Debug Toolkit

Hello, An Intel development kit DK-DEV-AGI027R1BES with the CXL Type 3 Example Design image causes an AMD Siena architecture system to reboot when a single write is issued. The information extracted...
Cxl
zutalors's avatar
zutalors
Icon for New Contributor rankNew Contributor
1 year ago

Are there any new information available on BIOS settings etc. on the EPYC platforms? I also ran into cyclic boot issues with the Siena and later migrated to Turin where I don't even get past the BIOS (it's cycling between the POST states 0x26,0x3F,0x3E). I'm also using the pre-built sof/pof files from the Type3 example design to rule out any build related errors on my side. I'm using the more recent RA version of the dev-kit. Any pointers would be appreciated.