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RicardoC's avatar
RicardoC
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

CXL IP Debug Toolkit

Hello, An Intel development kit DK-DEV-AGI027R1BES with the CXL Type 3 Example Design image causes an AMD Siena architecture system to reboot when a single write is issued. The information extracted...
Cxl
WZ2's avatar
WZ2
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi there，

Thank you for your concern. For some information on registers in the debug toolkit, you can refer to sections 5.13-5.14 in this document, as well as the official documentation for CXL.


https://www.intel.com/content/www/us/en/secure/content-details/795866/intel-agilex-7-r-tile-compute-express-link-cxl-1-1-2-0-fpga-ip-user-guide.html?DocID=795866


I am not questioning the source of your POF; rather, I am interested in the methodology you are using. Typically, we have not encountered situations where devices are not recognized by the system, and some of our customers also use AMD CPUs.

Best regards,

WZ