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RicardoC's avatar
RicardoC
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

CXL IP Debug Toolkit

Hello, An Intel development kit DK-DEV-AGI027R1BES with the CXL Type 3 Example Design image causes an AMD Siena architecture system to reboot when a single write is issued. The information extracted...
Cxl
WZ2's avatar
WZ2
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi Ricardo,

I apologize for the delay in responding due to health reasons; I am truly sorry for any inconvenience caused.

  1. Regarding the register, I understand that you wish to understand the values of CXL register internal registers for debugging. I can provide you with a register map for your reference. However, this document requires certain permissions. If you are unable to access it, please contact the Intel personnel who sold the board to you to obtain the necessary permissions:

https://www.intel.com/content/www/us/en/secure/content-details/777521/r-tile-intel-fpga-ip-for-compute-express-link-cxl-register-maps.html

  1. I am particularly interested in the first operation where the system cannot recognize the CXL device. For Type 3 operations, are you using avst to load the pof? If you only use sof, the system may not recognize the device, so please ensure that the CXL image is stored in the flash.

Best regards,

WZ