SJ_HwangNew Contributor11 months agoCXL ARB/MUX initialization debug Hi, I am currently implementing the CXL controller using the FPGA. (connected to Intel Xeon Sapphire Rapids Server) (I am not sure I am writing to the appropriate board. If I need to move this post...Show More
JYau1New Contributor27 days agoHi SJ,Did you manage to solve the issue? I'm running into the same problem.
Recent DiscussionsAbout Design Limitations and Known IssuesAbout Dual Simplex for Agilex 3Where is High Speed Transceiver Demo Design in FPGA Wiki ?Can't find Agilex 7 M I/O PLL Reconfiguration Design ExampleEnabling DFE Adaptation on Cyclone 10 GX