SJ_HwangNew Contributor1 year agoCXL ARB/MUX initialization debug Hi, I am currently implementing the CXL controller using the FPGA. (connected to Intel Xeon Sapphire Rapids Server) (I am not sure I am writing to the appropriate board. If I need to move this post...Show More
JYau1New Contributor5 months agoHi SJ,Did you manage to solve the issue? I'm running into the same problem.
Recent DiscussionsInquiry: Reference Clock Jitter Limits for 1G Operation on Agilex 5F-tile 10GBASE-R firecode FEC IP (Agilex 7)F-Tile Ethernet Hard IP Design Example - TestbenchWhere is High Speed Transceiver Demo Design in FPGA Wiki ?CORDIC ATan2 Failed to Generate