SJ_HwangNew Contributor1 year agoCXL ARB/MUX initialization debug Hi, I am currently implementing the CXL controller using the FPGA. (connected to Intel Xeon Sapphire Rapids Server) (I am not sure I am writing to the appropriate board. If I need to move this post...Show More
JYau1New Contributor8 months agoHi SJ,Did you manage to solve the issue? I'm running into the same problem.
Recent DiscussionsF-Tile PCIe Root Port 1x Gen3x4 - Configuration Read Type 0 receives no answermipi csi2 tx, upper limit of video widthDDR2 license QuestionF-tile ethernet hard ip in agilex7Cyclone IV GX PCIe Hard IP behaves differently on Intel Core I7 vs Xeon root complexes