SJ_HwangNew Contributor1 year agoCXL ARB/MUX initialization debug Hi, I am currently implementing the CXL controller using the FPGA. (connected to Intel Xeon Sapphire Rapids Server) (I am not sure I am writing to the appropriate board. If I need to move this post...Show More
JYau1New Contributor2 months agoHi SJ,Did you manage to solve the issue? I'm running into the same problem.
Recent DiscussionsRequest for private case.PCIe Enumeration Failure for CXL IPStratix-10G FPGA Transceiver Configuration for Ethernet MAC 100G ControllerRegarding the TX settings of MIPI CSI2 IPRegarding MIPI CSI 2 TX