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Altera_Forum's avatar
Altera_Forum
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14 years ago

CVI and vid_datavalid at separate syncs

Hi to all of you, I#m trying to bring up a self-made board. I have an Cyclone IV E. The FPGA is used only for Chroma Resampling from 4:4:4 to 4:2:2. At the moment I try to use an Tes...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hy Anja,

Try this: data_valid <= '0' when ((H = '1') or (V = '1')) else '1';