Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorCustom IP problem
Hai,
I am using Qsys to integrate all the custom IPs developed.I am using NiosII SBT to access the IPs. When i add a new IP to Qsys and try to access from Nios,its not working.Does anyone have these kind of probs? By adding a custom IP ,the nios ii goes to the reset state.who is actually resetting the nios?? I have seen that my IPs timing simulation works fine. Please help in this.15 Replies
Altera_ForumWhat board are you using?
- Altera_Forum--- Quote Start --- What board are you using? --- Quote End --- this is a custom made development board for Cyclone IV series.
- Altera_Forum--- Quote Start --- this is a custom made development board for Cyclone IV series. --- Quote End --- You may want to consider getting a sanity check on your Quartus/Qsys/NIOS projects using a commercial board. On your custom board, you need to check all of the usual things whenever you build a new board (power, clock, etc.) Your symptom sounds a lot like the FPGA itself is resetting or reconfiguring, possibly a board/design defect.
- Altera_Forum
Sir,
I have check the power level and the clock .That seems to be ok. Also with normal schematic file quartus project i am able to run the program in FPGA.But when i try to use the Nios,then only i am getting all these probs. If i am using the PIO's as output only.Then i am able to work with the project.But if i configure them as bidirectional and set its direction as output,then only its creating the problem. - Altera_Forum
Try single stepping through your software and watch relevant pins/PIO's in SignalTap to isolate your issue. For example, configure SignalTap to watch all your resets, all your PIO's and their Avalon-MM ports to watch the NIOS write something to them and cause the reset to occur.
