Hello We are porting Arria ii gx Nios processor in ddr2 IP and ddr2 clock feed from PLL C0 and PLL IP directly connected from FPGA clock I am facing some below critical warnings I google this ki...
Hello, I am trying to resolve critical warnings when using the DDR2 IP. I have noticed that the DDR2 Ref_clk is directly connected to the PLL_C0, which is set to output at 100MHz. I am unsure how to handle the Ref_clk if I export the ref_clk in platform designer, as it results in an error. Even when I export and use pll_c0 in the top level as connected ddr_clk , I encounter an error during compilation. I have come across the ALTCLKCTRL IP, but I am unsure how to implement it on top of my design. My question is, how can I solve these problems in handling the ref_clk for the DDR2 IP?
Occasional Contributor
