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nome's avatar
nome
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Critical Warning: PLL clock

Hello We are porting Arria ii gx Nios processor in ddr2 IP and ddr2 clock feed from PLL C0 and PLL IP directly connected from FPGA clock I am facing some below critical warnings I google this ki...
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sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
3 years ago

So again, the issue is the connection to the reference input to the PLL, also as discussed in the older thread you linked to. How is the input connected? It should be to a dedicated clock pin or from the output of another PLL.

  • nome's avatar
    nome
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    Hello

    Thanks for your Reply

    I am totally confuse about your question Sir I connect PLL clock with 50Mhz from FPGA main clock .

    maybe I can't recognize your question that's why I am sharing my project Archive

    please help me where I am wrong

    Please find attachment

    Thanks

    Nome