Critical Warning: PLL clock

Hello

Thanks for your Reply

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The warning is pretty self explanatory. It's not an SDC issue. As the message says, you're not driving the PLL from a dedicated clock input pin or from another PLL.

In QSYS Nios processor ALTPLL IP clock input already connected with main FPGA 50mhz clk50

I follow up this below discussion link but couldn't get remove these warnings

https://community.intel.com/t5/Intel-Quartus-Prime-Software/PLL-is-not-fully-compensated/m-p/554220

Below I am posting all our Critical Warnings

Critical Warning: PLL clock inst0_nios_cpu|lms_ctr_inst0|ddr2_1|lms_ctr_ddr2_1_controller_phy_inst|lms_ctr_ddr2_1_phy_inst|lms_ctr_ddr2_1_phy_alt_mem_phy_inst|clk|full_rate.pll|altpll_component|auto_generated|pll1|clk[1] driven through clock routing. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated clock pin on the same side.
Critical Warning: PLL clock inst0_nios_cpu|lms_ctr_inst0|ddr2_1|lms_ctr_ddr2_1_controller_phy_inst|lms_ctr_ddr2_1_phy_inst|lms_ctr_ddr2_1_phy_alt_mem_phy_inst|clk|full_rate.pll|altpll_component|auto_generated|pll1|clk[4] driven through clock routing. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated clock pin on the same side.
Critical Warning: PLL clock inst0_nios_cpu|lms_ctr_inst0|ddr2_1|lms_ctr_ddr2_1_controller_phy_inst|lms_ctr_ddr2_1_phy_inst|lms_ctr_ddr2_1_phy_alt_mem_phy_inst|clk|full_rate.pll|altpll_component|auto_generated|pll1|clk[1] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL.
Critical Warning: PLL clock inst0_nios_cpu|lms_ctr_inst0|ddr2_1|lms_ctr_ddr2_1_controller_phy_inst|lms_ctr_ddr2_1_phy_inst|lms_ctr_ddr2_1_phy_alt_mem_phy_inst|clk|full_rate.pll|altpll_component|auto_generated|pll1|clk[4] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL.
Critical Warning: PLL clock inst0_nios_cpu|lms_ctr_inst0|ddr2_1|lms_ctr_ddr2_1_controller_phy_inst|lms_ctr_ddr2_1_phy_inst|lms_ctr_ddr2_1_phy_alt_mem_phy_inst|clk|full_rate.pll|altpll_component|auto_generated|pll1|clk[1] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL.
Critical Warning: PLL clock inst0_nios_cpu|lms_ctr_inst0|ddr2_1|lms_ctr_ddr2_1_controller_phy_inst|lms_ctr_ddr2_1_phy_inst|lms_ctr_ddr2_1_phy_alt_mem_phy_inst|clk|full_rate.pll|altpll_component|auto_generated|pll1|clk[4] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL.
Critical Warning: PLL clock inst0_nios_cpu|lms_ctr_inst0|ddr2_1|lms_ctr_ddr2_1_controller_phy_inst|lms_ctr_ddr2_1_phy_inst|lms_ctr_ddr2_1_phy_alt_mem_phy_inst|clk|full_rate.pll|altpll_component|auto_generated|pll1|clk[1] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL.
Critical Warning: PLL clock inst0_nios_cpu|lms_ctr_inst0|ddr2_1|lms_ctr_ddr2_1_controller_phy_inst|lms_ctr_ddr2_1_phy_inst|lms_ctr_ddr2_1_phy_alt_mem_phy_inst|clk|full_rate.pll|altpll_component|auto_generated|pll1|clk[4] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL.
Critical Warning: PLL clock inst0_nios_cpu|lms_ctr_inst0|ddr2_1|lms_ctr_ddr2_1_controller_phy_inst|lms_ctr_ddr2_1_phy_inst|lms_ctr_ddr2_1_phy_alt_mem_phy_inst|clk|full_rate.pll|altpll_component|auto_generated|pll1|clk[1] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL.
Critical Warning: PLL clock inst0_nios_cpu|lms_ctr_inst0|ddr2_1|lms_ctr_ddr2_1_controller_phy_inst|lms_ctr_ddr2_1_phy_inst|lms_ctr_ddr2_1_phy_alt_mem_phy_inst|clk|full_rate.pll|altpll_component|auto_generated|pll1|clk[4] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL.
Critical Warning: PLL clock inst0_nios_cpu|lms_ctr_inst0|ddr2_1|lms_ctr_ddr2_1_controller_phy_inst|lms_ctr_ddr2_1_phy_inst|lms_ctr_ddr2_1_phy_alt_mem_phy_inst|clk|full_rate.pll|altpll_component|auto_generated|pll1|clk[1] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL.
Critical Warning: PLL clock inst0_nios_cpu|lms_ctr_inst0|ddr2_1|lms_ctr_ddr2_1_controller_phy_inst|lms_ctr_ddr2_1_phy_inst|lms_ctr_ddr2_1_phy_alt_mem_phy_inst|clk|full_rate.pll|altpll_component|auto_generated|pll1|clk[4] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL.
Critical Warning: PLL clock inst0_nios_cpu|lms_ctr_inst0|ddr2_1|lms_ctr_ddr2_1_controller_phy_inst|lms_ctr_ddr2_1_phy_inst|lms_ctr_ddr2_1_phy_alt_mem_phy_inst|clk|full_rate.pll|altpll_component|auto_generated|pll1|clk[1] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL.
Critical Warning: PLL clock inst0_nios_cpu|lms_ctr_inst0|ddr2_1|lms_ctr_ddr2_1_controller_phy_inst|lms_ctr_ddr2_1_phy_inst|lms_ctr_ddr2_1_phy_alt_mem_phy_inst|clk|full_rate.pll|altpll_component|auto_generated|pll1|clk[4] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL.
Critical Warning: PLL clock inst0_nios_cpu|lms_ctr_inst0|ddr2_1|lms_ctr_ddr2_1_controller_phy_inst|lms_ctr_ddr2_1_phy_inst|lms_ctr_ddr2_1_phy_alt_mem_phy_inst|clk|full_rate.pll|altpll_component|auto_generated|pll1|clk[1] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL.
Critical Warning: PLL clock inst0_nios_cpu|lms_ctr_inst0|ddr2_1|lms_ctr_ddr2_1_controller_phy_inst|lms_ctr_ddr2_1_phy_inst|lms_ctr_ddr2_1_phy_alt_mem_phy_inst|clk|full_rate.pll|altpll_component|auto_generated|pll1|clk[4] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL.
Critical Warning: Warning (307070): Input clock of the PLL nios_cpu:inst0_nios_cpu|lms_ctr:lms_ctr_inst0|lms_ctr_PLL_0:pll_0|lms_ctr_PLL_0_altpll_hcc2:sd1|pll7 must be fed by a dedicated input pin.
Critical Warning: Warning (307072): Input clock to the ALTMEMPHY PLL, nios_cpu:inst0_nios_cpu|lms_ctr:lms_ctr_inst0|lms_ctr_ddr2_1:ddr2_1|lms_ctr_ddr2_1_controller_phy:lms_ctr_ddr2_1_controller_phy_inst|lms_ctr_ddr2_1_phy:lms_ctr_ddr2_1_phy_inst|lms_ctr_ddr2_1_phy_alt_mem_phy:lms_ctr_ddr2_1_phy_alt_mem_phy_inst|lms_ctr_ddr2_1_phy_alt_mem_phy_clk_reset:clk|lms_ctr_ddr2_1_phy_alt_mem_phy_pll:full_rate.pll|altpll:altpll_component|altpll_r0p3:auto_generated|clk[1], when fed by another PLL, must come from the dedicated PLL to the PLL cascade path.
Critical Warning: Warning (307074): Source PLL, nios_cpu:inst0_nios_cpu|lms_ctr:lms_ctr_inst0|lms_ctr_PLL_0:pll_0|lms_ctr_PLL_0_altpll_hcc2:sd1|pll7, which is feeding the PLL, nios_cpu:inst0_nios_cpu|lms_ctr:lms_ctr_inst0|lms_ctr_ddr2_1:ddr2_1|lms_ctr_ddr2_1_controller_phy:lms_ctr_ddr2_1_controller_phy_inst|lms_ctr_ddr2_1_phy:lms_ctr_ddr2_1_phy_inst|lms_ctr_ddr2_1_phy_alt_mem_phy:lms_ctr_ddr2_1_phy_alt_mem_phy_inst|lms_ctr_ddr2_1_phy_alt_mem_phy_clk_reset:clk|lms_ctr_ddr2_1_phy_alt_mem_phy_pll:full_rate.pll|altpll:altpll_component|altpll_r0p3:auto_generated|clk[1], must have the compensation mode set to No Compensation instead of Normal
Critical Warning: Warning (307070): Input clock of the PLL nios_cpu:inst0_nios_cpu|lms_ctr:lms_ctr_inst0|lms_ctr_PLL_0:pll_0|lms_ctr_PLL_0_altpll_hcc2:sd1|pll7 must be fed by a dedicated input pin.
Critical Warning: Warning (307072): Input clock to the ALTMEMPHY PLL, nios_cpu:inst0_nios_cpu|lms_ctr:lms_ctr_inst0|lms_ctr_ddr2_1:ddr2_1|lms_ctr_ddr2_1_controller_phy:lms_ctr_ddr2_1_controller_phy_inst|lms_ctr_ddr2_1_phy:lms_ctr_ddr2_1_phy_inst|lms_ctr_ddr2_1_phy_alt_mem_phy:lms_ctr_ddr2_1_phy_alt_mem_phy_inst|lms_ctr_ddr2_1_phy_alt_mem_phy_clk_reset:clk|lms_ctr_ddr2_1_phy_alt_mem_phy_pll:full_rate.pll|altpll:altpll_component|altpll_r0p3:auto_generated|clk[3], when fed by another PLL, must come from the dedicated PLL to the PLL cascade path.
Critical Warning: Warning (307074): Source PLL, nios_cpu:inst0_nios_cpu|lms_ctr:lms_ctr_inst0|lms_ctr_PLL_0:pll_0|lms_ctr_PLL_0_altpll_hcc2:sd1|pll7, which is feeding the PLL, nios_cpu:inst0_nios_cpu|lms_ctr:lms_ctr_inst0|lms_ctr_ddr2_1:ddr2_1|lms_ctr_ddr2_1_controller_phy:lms_ctr_ddr2_1_controller_phy_inst|lms_ctr_ddr2_1_phy:lms_ctr_ddr2_1_phy_inst|lms_ctr_ddr2_1_phy_alt_mem_phy:lms_ctr_ddr2_1_phy_alt_mem_phy_inst|lms_ctr_ddr2_1_phy_alt_mem_phy_clk_reset:clk|lms_ctr_ddr2_1_phy_alt_mem_phy_pll:full_rate.pll|altpll:altpll_component|altpll_r0p3:auto_generated|clk[3], must have the compensation mode set to No Compensation instead of Normal
Critical Warning: Read Capture and Write timing analyses may not be valid due to violated timing model assumptions
Critical Warning: Read Capture and Write timing analyses may not be valid due to violated timing model assumptions
Critical Warning: See violated timing model assumptions in previous timing analysis above
Critical Warning: Read Capture and Write timing analyses may not be valid due to violated timing model assumptions
Critical Warning: See violated timing model assumptions in previous timing analysis above



Thanks
Nome

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