Creating a design with a 1G Ethernet IP for Synthesis

Hello QUARTUS IP experts,

I need to build a project which has a Triple Speed Ethernet IP in using QUARTUS Standard edition and Platform Designer. I can create an example design and i have been able to simulate that in QUESTA. But what is the best method to create a design which has the correct AVALON MM and AVALON ST modules connected up for the Control, Status, MDIO, and TX and RX paths ? Is there an ALTERA Github somewhere which already has this kind of test design built ? I am using a MAX10 FPGA and System Verilog.

My aim is to be able to synthesise and implement this test design so that i can see the LUT and memory utilizations a couple of different configuration, using the 1G speed.

Thanks for your help,

Barry