control QDRAMII SRAM [512k x 36 ,300MHZ] through IP core

Apparently, no QDRII support is available for Stratix III up to now.

But altmemphy has preliminary QDRII support, so you could design your own controller.

At first thanks for your reply .

My question is

does any documentation or sample exist , about how design a custom\[own]controller ???

Tx

See

http://download.cypress.com.edgesuite.net/design_resources/reference_designs/contents/altera_fpga_reference_design_18.pdf

and look around some more on the web - there may be a related app note from Cypress. My Cypress rep was able to get me some design files for their example as well.

But - 300 MHz will be a good challenge, even in Stratix III. We were satisfied to get 166MHz in Stratix II (we used 250MHz DDRII SRAMs, probably could have gotten 200MHz, but not much more).

QDRII+ may be a little easier to use, if like DDRII+ SRAM it provides a read ack flag with read data. But that comes with the cost of 1 more cycle of latency. The read ack flag does help with the clock crossings, mainly avoiding the need to calibrate any ring buffers.

\chuck

Thanks ,

I will see thisone .

1_ Could you send some project [ stratix2<->qdr2] to be able to simulte through modelsim application?

2_ What about the constrains , are those constrains possible to modify ?

Thanks,

Shush