Altera_Forum
Honored Contributor
17 years agoConstraint page in IP toolbench Megawizard
Hi There,
I generated the legacy DDR2 controller for StratixIIGX device using Megawizard. There is a constraint page in IP Toolbench. I am not able to understand the various fields on this page. I think that these fields must be constraining the pin assignments for DQ/DQS. I have got cetain pin assignments as per our board. How can I edit this page to constrain the pin assignments for DQ/DQs? Please suggest. Regards, Harsh Bandil