Connecting Wishbone I2C to NIOS2 in Qsys

I've performed this before in both SOPC and Qsys. Daixiwen is correct that it

can be performed by creating a new component and attaching a wrapper hdl source

file that links the Avalon signals to the Wishbone signals. SOPC/Qsys will

analyze this file and generate the signals needed.

An alternative method I use is to create a new component and link the core to

the NiosII system in the top level hdl source. The new component definition does

not include any source files. It has up to four interfaces defined for an

Avalon MM-Slave, clock input, reset input, and interrupt sender. The Avalon

MM-Slave interface should use addressAlignment NATIVE. Add signals for

writedata, readdata, address, chipselect, write, and waitrequest_n to the Avalon

MM-Slave interface. Add the clock, reset, and irq signals to their respective

interfaces. Then add this new component to the system contents in SOPC/Qsys.

The signals defined for this core will be added to the port I/O on the NisoII

system module.

The instantiation below is how I attached an I2C interface from OpenCores in

the top level source.

i2c_master_top# (.ARST_LVL(1'b0)) I2C_Master (

.wb_clk_i (clk_cpu),

.wb_rst_i (1'b0),

.arst_i (reset_n_to_the_I2C_Master),

.wb_adr_i (address_to_the_I2C_Master),

.wb_dat_i (writedata_to_the_I2C_Master),

.wb_dat_o (readdata_from_the_I2C_Master),

.wb_we_i (write_to_the_I2C_Master),

.wb_stb_i (chipselect_to_the_I2C_Master),

.wb_cyc_i (chipselect_to_the_I2C_Master),

.wb_ack_o (waitrequest_n_from_the_I2C_Master),

.wb_inta_o (irq_from_the_I2C_Master),

.scl_pad_i (scl_pad_i),

.scl_pad_o (scl_pad_o),

.scl_padoen_o (scl_padoen_oe),

.sda_pad_i (sda_pad_i),

.sda_pad_o (sda_pad_o),

.sda_padoen_o (sda_padoen_oe)

);