Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

connecting 32 bit data to 128 bit data with avalon

I think it maybe a silly problem but I can't get it work. I want to connect my master with 32 bit datawidth to a ddr controller with 128 datawidth using qsys. But when I simulate it in modelsim, it s...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Your picture is way too small, but the master must continue holding the command on the bus until waitrequest is deasserted. How long are you waiting before giving up on the command? Is there anything else going on in your system? Have you tried generating the example design with the parameters you mention to see how it simulates before connecting up to your own master?