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Honored Contributor
Honored Contributorconnecting 32 bit data to 128 bit data with avalon
I think it maybe a silly problem but I can't get it work. I want to connect my master with 32 bit datawidth to a ddr controller with 128 datawidth using qsys. But when I simulate it in modelsim, it s...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Hello, Have you tried to initiate any read or write operation? By default wait request from interconnect fabric will be high but when you initiate any read or write operation, it would go low. ( According to Avalon specification, read or write operation can be initiated even when wait request is high.) Cheers, Bhaumik --- Quote End --- Thankyou for your advance. http://www.alteraforum.com/forum/attachment.php?attachmentid=13444&stc=1 fifotest0 is my master and fifo20 is slave. The write request is asserted by master, but interconnection still asserts waitrequest. And my slave receives nothing, the write request is disasserted.
