New Contributor
Frequent Contributor
New ContributorKindly note that we are using Intel P-Tile AVMM IP for PCIe, not Intel P-Tile AVST IP for PCIe.
Frequent ContributorHi,
Kindly note the completion time out is been disabled in stratix 10 , irrespective of Avalon ST or MM
New ContributorCould you please make it clear? Does 'disabled' means
1)CTO value can't be changed. If so what's the default CTO value?
2)Completion Timeout won't happen. So the P-Tile IP for PCIe will wait for the response indefinitely
New Contributorwe are stuck at this point, kindly reply
Frequent ContributorHi,
CTO value can't be changed. If so what's the default CTO value?
>> I do not have a default value for the completion time out
2)Completion Timeout won't happen. So the P-Tile IP for PCIe will wait for the response indefinitely
No, Timeout will happen, the time out is implemented in HIP ( Hard Ip)
Only difference from other family of Intel FPGA devices is that , customer cannot change the Time out value ,. The Time out will happen by the default value in HIP.
