COMPLETION TIMEOUT CONFIGURATION IN P-TILE AVMM IP FOR PCIE

Question

I want to configure the completion timeout value of P-tile AVMM IP for PCIe. I didn't see any option to do so in the IP. Can anyone help me out with the issue?

rahul_s_intel1 · Answer

Hi ,
 It may be a known issue. Kindly find the KDB
https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/ip/2020/when-using-the-intel--fpga-p-tile-avalon--streaming-ip-for-pci--.html?wapkw=Completion%20timeout%20range

rkv · Answer

Kindly note that we are using Intel P-Tile AVMM IP for PCIe, not Intel P-Tile AVST IP for PCIe.

rahul_s_intel1 · Answer

Hi,
 Kindly note the completion time out is been disabled in stratix 10 , irrespective of Avalon ST or MM

rkv · Answer

Could you please make it clear? Does 'disabled' means 
1)CTO value can't be changed. If so what's the default CTO value? 
2)Completion Timeout won't happen. So the P-Tile IP for PCIe will wait for the response indefinitely

rkv · Answer

we are stuck at this point, kindly reply

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COMPLETION TIMEOUT CONFIGURATION IN P-TILE AVMM IP FOR PCIE

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