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Seadog's avatar
Seadog
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

compile error in A10 PCIe hard IP

I am getting this error message when elaborating a PCIe hard IP core with Avalon MM interface (build as a Qsys block with Platform Designer) Error(13224): Verilog HDL or VHDL error at altpcieav_dma_...
Seadog's avatar
Seadog
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

I have solved this problem. I built a PCIe endpoint with Avalon memory-mapped interface as .ip, rather than as a .qsys. Quartus allows this (and it seems to be fine for cores with the Avalon streaming interface), but it does not provide a way to program the BARs, i.e. to set the size of each addressable memory region. As a result, the BAR2_SIZE_MASK parameter is set to 0, and the upper index of rxm_address_reg[BAR2_SIZE_MASK -1:0] is a negative number (- 1). This causes the compile error.

The solution is to build a .qsys macro which contains just the PCIe core, and export the Avalon-MM master interfaces through bridges.