Comparison between DDR2 controller and high performance controller

First of all, apologies for delayed response. I have again carefully gone through Altera's reference designs (DDR2 for Arria II) and as far as I can tell, only 50% of SDRAM's capacity is utilized due to mismatch between DDR2 local bus size (128-bits) and PCIe data bus size (64-bits). To be precise:

1. DDR2 controller's 'local_rdata' port is mapped to 128-bit 'TxReadData' signal

2. Tx_Top's 'TxReadData_i' is mapped to 'TxReadData[63:0]'

which means that higher-order 64-bits of TxReadData are essentially discarded in this design.

I had also thought of reprogramming the DDR2 controller to 64-bit local bus width (i.e. 32-bit internal data bus) but that automatically reduces the memory size by 50% (as seen in Mega Wizard).

Has anyone run into these issues and what would be the easiest way to bypass this restriction? If anyone has tried, could you please let me know how much of an effort it would be to modify Tx_Top app logic to transmit 128-bit data over 64-bit bus?

Thanks,

Piyush