The following configuration seems to work correctly:
Test Pattern (seq. RGB) -> Median Filter -> Color Plane Seq. (Par. RGB) -> Clocked Video Output (Par. RGB)
With the following clocking:
Test Pattern = 3x video clock
Median Filter = 3x video clock
Color Plane Seq. = 3x video clock
CVO = 1x video clock
I get a nice test pattern out of the above.
Ok, so now I put the following into the data chain
CVI (par. RGB) -> CPS (seq. RGB) -> Median Filter -> CPS (par. RGB) -> CVO (par RGB)
With the following clocking:
CVI = 1x video clock
Color Plane Seq. = 3x video clock
Median Filter = 3x video clock
Color Plane Seq. = 3x video clock
CVO = 1x video clock
And this design fails - no switching on any of the video outputs at all, HSYNC, VSYNC and Valid all dead.
I would think its because the CVI -> CPS clocking is somehow incorrect where we would want the CPS to run at 1x video clock when going from parallel RGB to sequential RGB. What is the correct thing to do here as I cannot modify the CPS clock in the SOPC to account for this discrepancy.
Thanks,
Mike