Altera_ForumHonored Contributor13 years agoclocked video input , output Hi, In my design I try to simulate input video on fpga in the begin I connect test pattern to the output video and it work good then I generate test pattern and out with embbeded sync and c...Show Moreclock in out.jpg427 KB
Recent DiscussionsAgilex-7 AXI MCDMA for PCIe hangConstraints not being picked for DCFIFOCan't generate F-Tile Ethernet Hard IP Design ExampleMAX10 TSE reference designAccessing registers in the PCIE IP beyond MCDMA using system console