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Altera_Forum
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13 years ago

Clock input port inclk[0] of PLL Error

Hi, I have the following Problem: Error (15065): Clock input port inclk[0] of PLL "DE0_Nano_uCE0_Nano_uC_inst|clocks_0:the_clocks_0|altpll: DE_Clock_Generator_Audio|altpll_o152:auto_generated|...
Altera_Forum's avatar
Altera_Forum
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13 years ago

The error message is quite clear. What did you connecto to pll input port?

On DE0 Nano it should be the 50MHz clock getting into fpga pin R8.