clock frequency limit for ddr3 using EMIF ip on arria V fpga

Hi Sir,

Thank you for sharing the calibration result.

Based on past history, we did experienced glitches issue impacting the DQS as shown in the KDB here-->

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd06212015_557.html

I can see you are using Quartus version 16.1.2 Build 203, so it should be no problem.

The calibration is passing but the issue is more to signal integrity (SI). To be honest, there are many possible factors that can lead to SI issue. It could be due to your board termination, PCB routing, external noise, temperature, IP setting, board skew,.. etc. I will try my best to guide you and hopefully it helps.

My suggestions are as follow:

1) Please make sure the memory timing is fully comply with memory datasheet. Please note on the following dependent setting (picture is taken from other Quartus version). As you can see there are setting that depend on the frequency and temperature as well, thus it is important to make sure DDR3 settings and timing parameters in the GUI match the device specs in datasheet.

2) Next is board settings. As u mentioned, you are using the default setting in he GUI. The Altera default setting are representative for specific Altera’s board. Intel recommended to change this value based on your board level effects. Refer below:

• “Channel Signal Integrity”: This can cause signal distortion and reduction to timing margin. I recommend you to perform simulation and enter this value accordingly.
• “Board Skews”: This also another cause for reduction in timing margin. As the frequency increase, it is important to make sure this board skews are accurate during IP generation. Please use the latest board skew parameter tool to accurately calculate the board skews: https://www.altera.com/solutions/technology/memory/estimator/board-skew.html
• Same apply with the “Setup and Hold Derating” section.

I strongly believed you are using the correct termination at your board but just a double check. Please verify that the RZQ pin resistor is the correct value. For DDR3, the FPGA RZQ pin should connect to GND through 100 ohm resistor. For DDR3L, the resistor should be 240 ohms to GND.

You may find it useful to run the example design simulation and look at the waveforms to help understanding. 😊

Let me know if there is any concern.

Thanks

Regards,

Aida