Clarification of documentation for Align Packet Headers to 32-bit Boundaries option in TS-Ethernet

There are also the tx_cmd_stat and rx_cmd_stat registers:

The description for TX_SHIFT16 says "Set this bit if the frames from the user are aligned on a 32-bit boundary." But the Avalon streaming interface requires the first word of a packet to by a full word (the empty[n-1:0] field is ignored), so it is not clear how the frames could not be aligned on a 32-bit boundary., as the interface is 32 bits wide.

Also, are the TX_SHIFT16 and RX_SHIFT16 bits forced to a specific state by the Align Packet headers to 32-bit boundary option? The user guide only states what happens if there are no FIFOs in the core.