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Altera_Forum
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17 years ago

Clamshell Top and Bottom Device

Hi There Has anyone there got idea on clamshell top and bottom device. In my case the DDR2 device on altera board(StratixIIGX) has 14 address lines per clamshell with 3 bank address bits. ...
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Altera_Forum
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17 years ago

The datasheet is about a Xilinx dev kit, but is talking of independant DDR2 banks.

It may be the case, that the Altera version of the board, which apparently also exists, isn't compatible with present Altera DDR2 controller cores. You may need to contact the manufacturer regarding intended mode of operation and respective example designs for their boards.