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Honored Contributor

17 years ago

Clamshell Top and Bottom Device

Hi There Has anyone there got idea on clamshell top and bottom device. In my case the DDR2 device on altera board(StratixIIGX) has 14 address lines per clamshell with 3 bank address bits. ...

Altera_Forum

Honored Contributor

17 years ago

http://www.aliathon.com/c-nic_brief.pdf. Control signals are not shared between top and bottom device. Only address and bank signals are shared.

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Clamshell Top and Bottom Device

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