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Altera_Forum
Honored Contributor
Honored ContributorClamshell Top and Bottom Device
Hi There Has anyone there got idea on clamshell top and bottom device. In my case the DDR2 device on altera board(StratixIIGX) has 14 address lines per clamshell with 3 bank address bits. ...
Altera_ForumHonored Contributor
Honored Contributorhttp://www.aliathon.com/c-nic_brief.pdf. Control signals are not shared between top and bottom device. Only address and bank signals are shared.
