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Altera_Forum
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17 years ago

Clamshell Top and Bottom Device

Hi There Has anyone there got idea on clamshell top and bottom device. In my case the DDR2 device on altera board(StratixIIGX) has 14 address lines per clamshell with 3 bank address bits. ...
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Altera_Forum
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17 years ago

I didn't understand clearly from your post which pin assignment you're talking about. If the design is accessing two DDR2 bank with individual address and control lines, they must be operated by two individual controller instances. The Stratix II GX PCI Express Dev. Kit I know has a single bank with common address lines, however. Which board do you have? There are other Altera Dev. Kits with two individual DDR2 banks, but not Stratix II GX, as far as I know.