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CPoir's avatar
CPoir
Icon for New Contributor rankNew Contributor
6 years ago

CIC interpolator gives no output when stages are a power of 2

Hi folks, I'm trying to simulate a CIC interpolator. I noticed that when the number of stages is a power of 2 (1,2,4 or 8, since the maximum is 12), I only get zeroes as the output. Any other value ...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

Sorry for the delay. I have been performing a number of tests on my side. I observe that with default configuration of the CIC Interpolator (stage = 12, rate change = 8, rounding = none), there is no issue with the simulation output using IP generated example design in Q18.1Pro. As I cross check with your Interpolator.qsys, I notice that the number of stage is set to 1 in your configuration. As I tested setting stage = 1 and run the IP generate example design, I can observe output data and valid = 0. Based on these observation, we can narrow down to the parameter "Number of stages" set in your failing case. Would you mind to increase this parameter to 12 to see if it helps on your side?

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin