Can't get DDR2 ALTMEMPHY to work on Cyclone IV E

Greetings.

I am having some difficulty getting the Altera DDR2 ALTMEMPHY SDRAM controller to work on my Cyclone4E EP4CE30F23. I have configured the DDR2 controller to run in half-rate mode where the controller runs at 80/160 MHz which it derives from a 24 MHz input clock.

It all seems to build OK in SOPC Builder and Quartus and I don’t appear to be getting any timing violations.

The odd thing is that the presence of the DDR2 SDRAM controller somehow causes the on-chip SRAM to not function properly. I have tried running the CPU and the on-chip SRAM at 24MHz (the input clock frequency) and 80MHz (the half-clock generated by the DDR2 controller), but neither one works.

I have built a test project that contains only a NIOS2 CPU, a PIO, 32kB of on-chip RAM and the DDR2 controller. When I disable the DDR2 SDRAM controller (via the ‘Use’ column in SOPC builder), I can build and run NIOS2 code in the on-chip SRAM. When I enable the DDR2 SDRAM controller, I am no longer able to run code out of the on-chip SRAM. The Eclipse console window shows the following:

Using cable "USB-Blaster [USB-1]", device 1, instance 0x00

Processor is already paused

Initializing CPU cache (if present)

OK

Downloading 00010000 ( 0%)

Downloading 00010ED0 (60%)

Downloaded 4KB in 0.0s

Verifying 00010000 ( 0%)

Verify failed between address 0x10000 and 0x10907

Leaving target processor paused

Any help with this matter would be greatly appreciated.

I have attached the FPGA/BSP/App projects for my test application.

Thank you

Scott Wild