Can't find Agilex 7 M I/O PLL Reconfiguration Design Example

Hi,
Recently updated document
"Agilex™ 7 Clocking and PLL User Guide M-Series", 769001   2025.10.09
refers to a design example which uses an EMIF Calibration IP for I/O PLL reconfiguration:
6.1.7. Design Example for I/O PLL Reconfiguration

I can't find this design on Intel or Altera sites. Can anyone please tell if it exists. I can find very similar Agilex 7 PLL reconfig examples but they use different calibration IP, not usable with Agilex 7M devices.

I'm trying to utilize IOPLL's dynamic output phase adjustment only. This was easy with earlier generation devices as the I/O PLL provided a specific control interface for this purpose. Phase shift control port or something similar.

Thanks,
Ju-ti