Forum Discussion

Likewise's avatar
Likewise
Icon for New Contributor rankNew Contributor
7 years ago

Can we use 256 PCIe tags handled in soft-logic?

Hello all, I am reading contradictory information about the support for 256 tags with the PCIe HIP. We are using the HIP with it's ST RX/TX interface (Stratix V and newer), not any of the DMA-MM sof...
Nathan_R_Intel's avatar
Nathan_R_Intel
Icon for Contributor rankContributor
7 years ago
Hie Leon, In Stratix V PCIe Avalon ST interface configuration, 256 tags can be used but you will need to disable "Enable Hard IP completion tag checking". Our older Stratix V device only able to support validating completion tags when using 32 or 64 tags. So, your understanding is correct whereby you need to verify yourself is the completion tags match for non-posted request. What the feature "Enable Hard IP completion tag checking" is enabled; the HIP ensures there are not outstanding requst market with same tag. Hence, there wont be a case of reusing a tag from a read request untill receiving the read response for that request. Regards, Nathan.
Likewise's avatar
Likewise
Icon for New Contributor rankNew Contributor
7 years ago

Thank you.

In newer datasheets it is mentioned that Configuration Bypass mode is required for 128 or 256 tags. Why is that? Is it because the 256 tags support must be announced by soft-logic as well, instead of by the HIP?

One question to clearify: You wrote "In Stratix V...256 tags can be used..." and then in the 2nd sentence "Our older Stratix V...only...64 tags". I assume Stratix V can only validate up to 64 tags in its PCIe HIP (more tags must be moved into soft-logic). Newer devices (Arria 10 and Stratix 10) do support 256 tags in HIP?

Currently I am targeting Stratix V GX.