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Likewise's avatar
Likewise
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7 years ago

Can we use 256 PCIe tags handled in soft-logic?

Hello all,

I am reading contradictory information about the support for 256 tags with the PCIe HIP. We are using the HIP with it's ST RX/TX interface (Stratix V and newer), not any of the DMA-MM soft-logic provided by Intel.

According to the documentation, 256 tags can be enabled in the HIP, only if our (soft-logic) "Application Layer" validates the completion tags. This is what we want to use. Is this option available?

What is meant by "validating completion tags"? Does it mean we should verify that the completion tags match with our non-posted requests (such as MRd)? Should we signal an error if not?

The other case is where the HIP validates the completion tags, but that leaves only 32 or 64 tags. What does the HIP do to validate the completion tags?

Thank you,

Leon.

Feb 2nd 2019

5 Replies

  • Nathan_R_Intel's avatar
    Nathan_R_Intel
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    7 years ago
    Hie Leon, In Stratix V PCIe Avalon ST interface configuration, 256 tags can be used but you will need to disable "Enable Hard IP completion tag checking". Our older Stratix V device only able to support validating completion tags when using 32 or 64 tags. So, your understanding is correct whereby you need to verify yourself is the completion tags match for non-posted request. What the feature "Enable Hard IP completion tag checking" is enabled; the HIP ensures there are not outstanding requst market with same tag. Hence, there wont be a case of reusing a tag from a read request untill receiving the read response for that request. Regards, Nathan.
    • Likewise's avatar
      Likewise
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      7 years ago

      Thank you.

      In newer datasheets it is mentioned that Configuration Bypass mode is required for 128 or 256 tags. Why is that? Is it because the 256 tags support must be announced by soft-logic as well, instead of by the HIP?

      One question to clearify: You wrote "In Stratix V...256 tags can be used..." and then in the 2nd sentence "Our older Stratix V...only...64 tags". I assume Stratix V can only validate up to 64 tags in its PCIe HIP (more tags must be moved into soft-logic). Newer devices (Arria 10 and Stratix 10) do support 256 tags in HIP?

      Currently I am targeting Stratix V GX.

  • Nathan_R_Intel's avatar
    Nathan_R_Intel
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    7 years ago
    Hie, The "Configuration Bypass mode" is required for 128 or 256 tags in only applicable for Arria 10 and Cyclone 10 devices. Refer to link below: https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/ip/2018/why-does-the--number-of-tags-supported--parameter-does-only-show.html Arria 10 similar to Stratix 10 requires "Application Layer" to validate the completion tags for 256 tags support. However, Stratix 10 HIP does support 256 tags without requiring application layer to perform completion tag checking. Regards, Nathan
  • Likewise's avatar
    Likewise
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    7 years ago

    > The "Configuration Bypass mode" is required for 128 or 256 tags in only applicable for Arria 10 and Cyclone 10 devices.

    Thanks. Does that also apply for "Stratix V GX" devices?